CDCVF2509A driver equivalent, 3.3-v phase-lock loop clock driver.
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* Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
* Spread Spectrum Clock Compatible
* Operating Frequency 20 MHz to 175 MHz
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* Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
* Separate Output Enable for Each.
The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed fo.
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